1. Field of the Invention
The present invention relates to electronic timers for generating precise timing signals. More particularly, the invention concerns a ramp circuit that uses charge balancing to achieve improved ramp signal linearity, enabling faster retriggering.
2. Description of the Related Art
Electronic timers are widely used in many different applications. For example, electronic clocks generate carefully defined, high speed clock cycles necessary to operate digital computers. Timers are also an integral component of test circuits that measure and evaluate operational characteristics of circuits such as memory, microprocessors, high speed logic circuits, and the like. This type of test circuit is often implemented in an automatic test equipment board, which frequently includes both digital and analog circuits.
In this context, engineers have developed a class or circuits called "timing verniers", which provide finely adjustable timing signals. Timing verniers are often sold as a "macro" item, selected by a customer for use in an application specific integrated circuit along with other desired components.
There are many known timing verniers, one class of which is exemplified by the model PDS01S product manufactured by Applied Micro Circuits Corp. (AMCC). This class of timing vernier includes a number of components, shown in simplified block form in FIG. 1. Namely, the timing vernier 100 includes a ramp 102, digital-to-analog converter (DAC) 104, comparator 106, and threshold sensor 114. The ramp 102 produces an analog voltage signal (at output 103) that decreases at a prescribed linear rate. The signal at the output 103 may also be called a "ramp" signal. The DAC 104 provides a fixed analog timing signal select (at output 110) according to a digital timing select input signal (at input 108). When the comparator 106 determines that the ramp's decreasing output signal (at 103) reaches the fixed analog timing select signal 110, the comparator 106 produces a timing event. The timing event is a characteristic of the timing output signal, and may comprise a pulse, digital signal transition (i.e., high-to-low or low-to-high), or another recognizable signal characteristic. When the threshold sensor 114 determines that the ramp's decreasing output signal (at 103) matches the fixe reset select signal on the line 115, the sensor 114 issues a reset signal to the ramp 102, causing the ramp 102 to bring its output back to a predetermined starting level.
FIG. 2 depicts a timing diagram illustrating the operation of the timing vernier 100. The output 103 of the ramp 102 is shown by the waveform 200. Starting from a predetermined starting value 222, the waveform 200 then provides an analog voltage decreasing at a constant level throughout a region 202 of the waveform 200. Several alternative analog timing select signals 110 are shown by the levels 204-206. Each different analog timing select signal is produced by changing the voltage of the digital timing select input signal 108. Different analog timing select signals produce timing events that occur at different times.
For example, if the digital timing select signal 108 is chosen to provide an analog timing select signal 204, the comparator 106 detects when the ramp signal 200 reaches the level 204 when this occurs, the output 112 of the comparator 106 exhibits a timing signal 208 including the timing transition 210. As a different example, the digital timing select signal 108 may be set to yield an analog timing select signal at the level 205. In this case, when the comparator 106 detects the ramp signal 202 reaching the level 205, the output 112 of the comparator 106 exhibits a timing signal 212 including the timing transition 214. Alternatively, the digital timing select signal 108 may instead be set to yield an analog timing select signal at the level 206. In this case, when the comparator 106 detects the ramp signal 202 reaching the level 206, the output 112 of the comparator 106 exhibits the timing signal 216 with the timing transition 218.
As shown in FIG. 1, the threshold sensor 114 is provided to recognize when the output signal 103 of the ramp 102 reaches a fixed threshold value 220, set by the input 115. When the output signal 103 reaches the value 220, the threshold sensor 114 resets the ramp 102, causing the ramp 102 to increase its output back to the predetermined starting value 222 (FIG. 2). There may be some delay in reaching the steady-state value 222 due to overshooting and/or ringing that occurs in a region 224 of the waveform 200.
Although known timing verniers such as the foregoing constitute significant advances and enjoy widespread commercial success today, AMCC has continually sought to improve the performance and efficiency of their timing verniers. One area of particular focus is the speed and signal resolution of timing signals. All timing verniers produce timing signals whose frequency is subject to some maximum value, beyond which the resultant timing signal may unreliable. If the timing signal is not sufficiently fast or crisp in definition, the circuit using the timing signal may produce inaccurate data.
Nonetheless, with the ever-increasing operating speeds of circuits to be tested, it is increasingly important to have timers that provide faster and more clearly defined timing signals. Consequently, advances are continually needed to boost the speed and resolution of timing signals.